The Electronic devices group performs research in integrated circuit design and physics of electronic devices. The research has close connection to graduate and undergraduate education. Our general goal is to combine physical science and electrical engineering in the field of physical electronics and related applications for further use in industrial products.
19 persons are engaged in the research program, of which eleven are graduate students. Additionally, five external graduate students (not employed at the group) are engaged.
One graduate course was given during spring, Microelectronic Systems (Christer Svensson).
The group has mainly been financed by four research consortia, aimed at collaboration between academia and industry, and financed through Foundation for Strategic Research (SSF), "Advanced System Design with ASIC", "High-Speed Electronics", "IR Sensors" and "Smart Sensors". These consortia are a new form of research collaboration in Sweden, originally proposed by Christer Svensson. The group is furthermore financially supported by the Center for Industrial Information Technology (CENIIT) at Linköping university, by the Swedish Research Council for Engineering Sciences (TFR), by Intel corporation and by ECSEL graduate school at Linköping university.
Christer Svensson is associate editor of IEEE Journal of Solid-State Electronics and has served in the program committees of the European Solid State Circuit Conference (ESSCIRC) 1998 and the International Solid State Circuits Conference (ISSCC) 1999 (European subcommittee). Per Larsson-Edefors served in the program committee of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 1998. Christer Svensson is also a member of the Working group for Microelectronics within SSF.
Two of our students, Atila Alvandpour and Peter Hazucha, spend 3 months during summer 1998 at Intel in Hillsboro, Oregon, as internships.
During 1998 Christer Svensson developed a proposal for a new national research program, Integrated Electronic Systems, financed by SSF, and replacing some of the consortia mentioned above. The new program will start Jan. 1, 1999.
During 1998 the group has published 14 journal papers, 22 papers in international conferences and one book chapter. Two patent applications have been filed.
We have studied high-performance CMOS circuit techniques and methodology. This project is a part of the Advanced System Design with ASIC (AASICCS) consortium, in cooperation with Ericsson CADLAB, Saab Dynamics and Lund University (Per Andersson) and a part of the High-Speed Electronics consortium in cooperation with Ericsson HSERC, Ericsson MIRC, Saab Dynamics and the National Defence Research Establishment (FOA).
High-speed electronics is very useful in the context of high-speed networks. Christer Svensson was invited to give a talk on high-speed electronics in high-speed networks at Rank Prize Funds Minisymposium on Ultrafast Photonic Processing and Networks, England, April 20-23, 1998, and also at European commission LTR Workshop – Future Challenges in Microelectronic Design, Bruxelles, Belgium, March 19-20, 1998.
We have studied techniques and methods for 1..10 Gb/s data transfer between chips in high-speed systems. We have made a comprehensive analysis of high-speed data sampling using MOS transistors, and developed and measured some circuits demonstrating 7-16 GS/s sampling rate of digital data. We also developed a new phase-frequency detector for PLL’s. A comparison between electrical and optical interconnect, from a power consumption point of view, was performed, indicating that electrical interconnect is preferred for short distances.
A new architecture for high data throughput circuits was developed and demonstrated. One application is for data transport termination circuits, e.g. for SDH/SONET links. Other applications are for direct digital frequency synthesis (DDS) and for correlators for signal processing. Several application circuits were demonstrated.
As a part of the above-mentioned AASICCS consortium, we have developed an ATM switch chip, allowing several 10 Gb/s channels per chip. Several new techniques were developed for that purpose; a multiphase clock generator, techniques for optimization of wire drivers, techniques for pulse-width control in buffers and a layout-based schematic method for cell design. Also, the demonstrator itself, the ATM chip, was fabricated and investigated. So far, only limited functionality has been observed on the experimental chip.
A new principle for adaptive phase-adjusting data on input ports has been developed for several different applications and investigated in several implementation forms. This method is expected to be very useful for chip-to-chip communication at high (>500 MHz) clock frequencies, but can also be used on chip at high clock frequencies.
In order to efficiently match DSP units to A/D conversion (ADC), a set of new arithmetic circuits have been developed in collaboration with the DSP group at UCC, Ireland. The circuits operate in an MSB-first manner, thus allowing for simple interfacing to pipelined and successive approximation ADC. The three types of arithmetic circuits, performing multiplication, division and square-root respectively, can be optimized for operation on a single bit stream by use of a new interleaving approach.
A new, miniature serial-data SIMD architecture, which relies on use of interleaving and memory-cell delay elements, have been proposed.
We have developed a recursive filter structure, which utilizes a skewed pipeline to circumvent the sampling rate limitation. With the new structure it is possible to design filters that accept more than one sample per clock cycle.
Low-power electronics is a rapidly growing research area, motivated both by the increased power problems in high-performance chips and by the increased importance of high-performance battery-operated equipment. This project is partly linked to the AASICCS consortium (see previous research project). It is also financially supported by CENIIT at Linköping university, by TFR, and by Intel corporation.
Christer Svensson and Atila Alvandpour gave an invited paper at International Symposium on Low-Power Electronics and Design (ISLPED), Monterey, USA, Aug. 10-12, 1998, on low-voltage circuit techniques. Also, Christer Svensson and Jiren Yuan published an invited book chapter on IEEE press. Christer Svensson organized a panel at ISSCC 1998 on "Deep Sub 1V, SOI or Bulk CMOS?" and participated in a panel at ISLPED 1998 on "Past and Future Blockbusters in Low-Power Design".
Several basic issues concerning low-power design have been investigated. A new method for wire-length estimation at high levels of abstraction, for the purpose of power estimation, has been developed. The method has also been used in a tool developed at another department. Short-circuit power consumption has been investigated, and a new method for estimation of the short-circuit power consumption from measurements or analog simulations has been developed. Finally, the effect of Miller capacitance on the power consumption was analyzed.
A low-power phase accumulator was developed. The principle for reducing power consumption relies on a trade-off between accuracy and power.
We have commenced an investigation into modeling of RTL components. The goal of this project is to accompany the wire estimation technique, so as to create a complete technique for power consumption estimation at RT level.
Analog to digital converters
(M Duppils, J-E Eklund, K Folkesson, D Jakonis and C Svensson)
This project was a part of the High-Speed Electronics consortium (see the project High-performance digital CMOS circuitry) and is supported by Ericsson Components and ECSEL graduate school (Duppils).
In the area of high-speed A/D conversion, we are working in close cooperation with Ericsson Components, through Eklund, who is an Ericsson employee with his office at our place. We are planning a renewal of our research, by addressing issues of AD converter modeling, investigating basic limits to AD-converters and developing error correction techniques for ADC´s.
A new principle for a radio frontend, based on simultaneous switched capacitor channel filtering and A/D conversion, is under investigation, and the first test chips has been fabricated.
Basic physical limitations of electronics have always been studied by the group, as a basis for future research planning. Recently, we have deepened these studies in one subfield, that of effects of cosmic radiation on ordinary (non-space) electronics. This is motivated by the fact that natural neutron radiation is becoming increasingly important as technologies are scaled down in geometry and supply voltage. Several studies have been performed of the effect of natural radiation on electronics in aircrafts and using artificial neutron sources. Measurements and modeling of neutron induced errors, and the dependence on supply voltage, in memories designed by us has been done This research is supported by ECSEL graduate school (Hazucha), Ericsson Saab Avionics and European Office of Aerospace Research and Development.
Infrared image sensors
(D Jakonis , C Jansson, U Ringh and C Svensson)
This is a part of the infrared camera consortium and is run in cooperation with the National Defence Research Establishment, AGEMA and Royal Institute of Technology. In the infrared camera project our task has been to develop readout electronics for a focal-plane based on an array of bolometers. For this purpose we have developed readout circuitry connected to an array of high resolution A/D converters. During 1998, we have had a breakthrough in this research, in that several small demonstrators, including detectors, has been successfully demonstrated. We have started a more fundamental study, with the aim to compare different readout methods.
High-speed analog circuits
(M Danestig, R Malmqvist, S Rudner and C Svensson)
High-Q active MMIC filters have very low tolerances for temperature drift and process parameter variations. In a theoretical analysis we showed how these problems limit the Q-value of standard recursive active MMIC filters to values in the range of 30 to 100 and suggested some methods to improve these values.
Two different types of tunable recursive MMIC filters working at X-band have been implemented for evaluation. The first filter type uses an analog transmission-type phase shifter as tuning element resulting in a tuning range of 9% and an instantaneous filter bandwidth of only 1.2%. The second filter uses a novel, small-size three-bit time shifter as tuning element and has a tuning range as large as 16% and an instantaneous bandwidth of 5%.
We are currently investigating noise and dynamic range of such filters and how they can be integrated in single-chip radar frontend receivers.
High-frequency wide-bandgap semiconductor power devices
(E Janzén, S Rudner, C Svensson, Q ul Wahab)
This project contains three parts. Modeling of SiC high-speed devices using a commercial device simulation program, Medici. The idea is to optimize the device structure for applications at the high-frequency range of above 10 GHz, and to get optimum power due to the materials’ physical properties such as higher breakdown field and high thermal conductivity. Modeling of the device in its circuit, in order to better understand how to achieve highly efficient transmitters. In the third part, semi-insulating SiC substrates and thin film deposition is underway in the Material physics group at IFM headed by Prof. Erik Janzen. Processing of devices and electrical characterization is planned, as a joint effort between IFM at LiU, Microwave department at Chalmers Univ., (headed by Prof. Herbert Zirath) and FOA Linköping.
Publications
P Hazucha, K Johansson, and C Svensson: "Neutron Induced Soft Errors in CMOS Memories Under Reduced Bias". IEEE Transaction on Nuclear Science, vol.45 Dec 1998
H O Johansson and C Svensson: "Time resolution of NMOS sampling switches" IEEE Journal of Solid-State Circuits, vol. 33, pp. 237-245, Feb. 1998.
H O Johansson and C Svensson: "A simple precharged CMOS phase-frequency detector" IEEE Journal of Solid-State Circuits, vol. 33, pp. 295-299, Feb. 1998.
K Johansson, P Dyreklev, B Granbom, M C Calvet, S Fourtine, O Feuillatre: "In-Flight and Ground Testing of Single Event Upset Sensitivity in Static RAMs". IEEE Transaction on Nuclear Science, vol.45 no.3 June 1998 p. 1628-1632
K Johansson, P Dyreklev, B Granbom, N Olsson, J Blomgren, P-U Renberg: "Energy Resolved Neutron SEU Measurement from 22 to 160 MeV". IEEE Transaction on Nuclear Science, vol.45 Dec 1998
P Larsson-Edefors and W P Marnane: "Most-Significant-Bit-First Serial/Parallel Multipliers". IEE Proceedings - Circuits, Devices and Systems, vol. 145, no. 4, pp. 278-84, Aug. 1998.
S J Bellis, W P Marnane and P Larsson-Edefors: "Bit Serial, MSB First Processing Units". Intl J. of Electronics, in press.
P Larsson-Edefors: "A High-Speed Repeater Chain Interconnection in CMOS". IEEE Trans. on Circuits and Systems, I: Fundamental Theory and Applications, in press.
F Mu and C Svensson: "A Layout Based Schematic Method for Very High Speed CMOS Cell Design". Accepted by IEEE Trans. on VLSI systems.
F Mu and C Svensson: "Delay Calculation of Long Wire Interconnections for Uniform Line Driver". Accepted by IEEE Trans. On Circuit and Systems, Part I.
F Mu, A Edman and C Svensson: "Multiphase Digital Clock/Pattern Generator". Accepted by IEEE Journal of Solid-State Circuits.
J Yuan, and C Svensson: " Multigigahertz Circuits in Deep Submicron CMOS" , accepted for publication in Physics Scripta.
Z Ajaltouni, et al: "Evaluation of FERMI read-out of the Atlas Tilecal prototype", Nuclear Instruments & Methods in Physics Research, Section A, vol.403, p. 98-114, 1998.
E Berglind, L Thylen, B Jaskorzynska and C Svensson: "A Comparison of Dissipated Power and Signal to Noise Ratios in Electrical and Optical Interconnects", accepted for publication in Journal of Lightwave Technology, 1998.
A Alvandpour, P Larsson-Edefors and C Svensson: "Separation and Extraction of Short- Circuit Power Consumption in Digital CMOS VLSI Circuits", Proceedings 1998 International Symposium on Low Power Electronics and Design, pp. 245-249 , Monterey, CA , USA - August 10-12, 1998.
A Alvandpour, P Larsson-Edefors and C Svensson: "Impact of Miller Capacitance on Power Consumption", Proc. of Intl Workshop on Power and Timing Modelling, Optimization and Simulation, pp. 83-92, Lyngby, Denmark, Oct. 7-9 1998.
A Edman, A Björklid, and I Söderquist: "A 0.8 µm CMOS 350 MHz Quadrature Direct Digital Frequency Synthesizer with Integrated D/A Converters". Digest of technical papers 1998 Symposium on VLSI Circuits, pp. 54-55, 1998
H O Johansson: "7 Gbit/s measurements on a 0.8 µm CMOS line receiver", in Proc. ISCAS'98, Int. Symp. on Circuits and Systems, Monterey CA, May 31-June 3, 1998, paper WPA15-1.
H O Johansson and C Svensson: "16-Gbit/s measurements on a 0.8 µm CMOS sub-sampling circuit", in Proc. ESSCIRC'98, European Solid-State Circuits Conf., Haag, Netherlands, Sept. 22-24, 1998, pp.124-127.
M Ohlsson, P Dyreklev, K Johansson, P Alfke: "Neutron Single Event Upset in SRAM-Based FPGAs". IEEE Radiation Effects Data Workshop 1998
P Larsson-Edefors: "A Miniature Serial-Data SIMD Architecture", Proc. Of 1998 Euromicro Conf., vol. 1, pp. 341-4, Västerås, Sweden, Aug. 25-27 1998.
F Mu and C Svensson: "A 750Mb/s 0.6 µm CMOS Two-phase Input Port Using Self-Tested Self-Synchronization". To be presented at 1999 International Solid-State Circuits Conference, San Francisco, USA, Feb.,16, 1999.
F Mu and C Svensson: "Efficient High Speed CMOS Design by Layout Based Schematic Method". Proceedings of the 24th EuroMicro Conference, Vol. 1, pp.337-340, Västerås, Sweden, Aug., 25-27, 1998
F Mu and C Svensson: "A Digital Clock Generator for an ATM Switch Implemented with Multiphase Clock". Proceedings of the 24th European Solid-State Circuit Conference, pp.148- 151, Sept., 22-24, Haag, Netherlands, 1998
F Mu and C Svensson: "Self-Tested Self-Synchronization by a Two-Phase Input Port for High Speed ULSI Design". Proc. Of International ASIC Conference, pp.462-467, (Invited paper), Beijing, China, Oct., 22-26, 1998.
F Mu and C Svensson: "Self-Synchronized Vector Transfer for Parallel Systems". 1998 International Conference on Parallel and Distributed Systems, Taiwan, Dec., 14-16, 1998,
F Mu and C Svensson: "Self-Tested Self-Synchronization by a Two-Phase Input Port ". Proceedings of the 11th Annual IEEE International ASIC Conference, pp., 259-262, Rochester, NY, USA, Sept., 13-16 1998.
F Mu and C Svensson: "High Throughput Vector Transfer by Self-Tested Self- Synchronization for Large Parallel Systems". 1998 International Conference on Parallel and Distributed Computing and Networks, Brisbane, Australia, Dec., 14-16, 1998.
F Mu and C Svensson: "High Speed Interface for System-on-Chip Design by Self-Tested Self-Synchronization". Accepted by The 1999 IEEE International Symposium on Circuits and Systems.
F Mu and C Svensson: "High Speed Multistage CMOS Clock Buffers with Pulse Width Control Loop". Accepted by the 1999 IEEE International Symposium on Circuits and Systems.
F Mu and C Svensson: "Methodology of Layout Based Schematic and Its Usage in Efficient High Performance CMOS Design" Accepted by The 1999 IEEE International Symposium on Circuits and Systems.
M Danestig, A Ouacha, C L K Tsoen, T Tieman, and S Rudner: "Recursive filters employing transmission type phase shifters and novel self-switched time shifters for freguency tuning". Proceedings of the 28th European Microwave Conference, Amsterdam, October 5-9, 1998, pp 352-357.
C Svensson: "The limits to high-speed electronics", Invited, 11th International Conference on Integrated Optics and Optical Fibre Communications and 23rd European Conference on Optical Communications, IOOC-ECOC 97 (Conf. Publ. No.448), vol. 4, pp. 85-88, 1997.
C Svensson: "The Limits to High Speed Electronics", Invited, The Rank Prize Funds Minisymposium on Ultrafast Photonic Processing and Networks, Grasmere, England, April 20-23, 1998.
F Mu, A Alvandpour and C Svensson: "Linearized sub-optimum method of long wire interconnections with uniform wire driver". Proceedings of the 1998 IEEE International Symposium on Circuits and Systems, Vol 2, pp. 252-5, 1998
C Svensson and A Alvandpour: "Low Power and Low Voltage CMOS Digital Circuit Techniques". Proceedings 1998 International Symposium on Low Power Electronics and Design, pp. 7-10 , Monterey, CA , USA - August 10-12, 1998.
C Svensson and J Yuan: "Latches and Flip-Flops for Low Power Systems", in Low Power CMOS Design, A Chandrakasan and R Brodersen, eds., IEEE Press, 1998.
A Alvandpour, P Larsson-Edefors and C Svensson: "Design-Sensitive Interconnection Length Estimation".
A Alvandpour, P Larsson-Edefors, and C Svensson: "Design-Sensitive Interconnection Length Estimation". Submitted to IEEE Transactions on very large scale integrated systems.
M Duppils, J-E Eklund, and C Svensson: "Development of a Single-Chip Radio Receiver in CMOS Technology", CCSSE'98, Sweden.
A Edman and P Larsson-Edefors: "Parallel Recursive Filters based on Skewed Pipelines".
A Edman, B Rudber, and C Svensson: "Unidirectional Pipelined Data Path Architecture with Applications in 10-Gb/s SONET/SDH Processing" (manuscript)
A Edman, J Christensen, and A Emrich: " A Low Power 416-lag 1.5-b 0.5-TMAC Correlator in 0.s A Low Power 416-lag 1.5-b 0.5-TMAC Correlator in 0.6-µm CMOS" (manuscript)
A Edman: "A 2.4-Gb/s 4:1 Multiplexer in 0.8 µm CMOS" (manuscript)
H Eriksson, A. Edman and P. Larsson-Edefors: "A Multiplexer-Based Low-Power Phase Accumulator".
R Malmqvist, M Danestig, S Rudner, and C Svensson: "A theoretical analysis of sensitivity and Q-value for recursive active microwave integrated filters". IEE proceedings Microwaves, Antennas and Propagation, submitted (1998)
F Mu and C Svensson: "Pulse Width Control Loop in High Speed CMOS Clock Buffers". Submitted to IEEE Journal of Solid-State Circuits.
F Mu and C Svensson: "Self-Tested Self-Synchronization by a Two-Phase Input Port for High Speed ULSI Design". Submitted to IEEE Trans. on VLSI Systems.
F Mu and C Svensson: "A Semi-Synchronous Method for High Speed Large Systems". Submitted to IEEE Journal of Solid-State Circuits.
F Mu and C Svensson: "Self-Synchronized Vector Transfer for Parallel Systems". Submitted to IEEE Trans. on Parallel and Distributed Systems.
F Mu and C Svensson: "A New Two-phase Input Port Using Self-Tested Self-Synchro- nization". Submitted to IEEE Journal of Solid-State Circuits.
F Mu, and C Svensson: "Layout Based Schematic and Its Usage in Very High-Speed CMOS Design". Rapport IFM-R-221
Ted Johansson: The transistor, with emphasis on its use for radio frequency telecommuni- cation. Linköping Studies in Science and Technology. Dissertations No 508
Henrik Johansson: CMOS Parallel-Sampling Receivers. Linköping Studies in Science and Technology. Dissertations No 540
Anders Edman: High Data Throughput CMOS Circuits. Linköping Studies in Science and Technology. Dissertations No 545
Atila Alvandpour: Low Power Design and Estimation Techniques for digital VLSI Circuits. Linköping Studies in Science and Technology. Licentiate Thesis No 698
F Mu and C Svensson: "Anordning och metod för att synkronisera data till en lokal klocka". Svensk patentansökan 9803100-8.
J-E Eklund, and A Edman: "Analog till digital omvandlare med seccessiv approximation". Svensk patentansökan nummer 9801367-5