Annual report 1999



The Electronic devices division performs research in integrated circuit design and physics of electronic devices. The research has close connection to graduate and undergraduate education. Our general goal is to combine physical science and electrical engineering in the field of physical electronics and related applications for further use in industrial products.

In the end of 1999, 18 people, of which ten are graduate students, are engaged in research and teaching. Additionally, five external graduate students (not employed at the group) are engaged.

Staff (Dec. 31, 1999)

Christer Svensson
Ingegärd Andersson
Associate professors
Per Larsson-Edefors
Dake Liu
Adjunct professor
Staffan Rudner
Research assistant
Quamar ul Wahab
Guest researcher
Jan-Erik Eklund
Christer Jansson
Senior research engineer
Arta Alvandpour
Graduate students
Håkan Bengtson
Mattias Duppils
Daniel Eckerbert
Henrik Eriksson
Kalle Folkesson
Peter Hazucha
Tomas Henriksson
Darius Jakonis
Robert Malmqvist
Ulf Nordqvist
External graduate students
Magnus Danestig
Karin Johansson
Ulf Ringh
Joakim Strömberg
Ingemar Söderqvist

Graduate education

During 1999, the division has produced two doctors and three licentiates. On Feb. 26, 1999, M.Sc. Fenghao Mu defended his doctoral thesis entitled "Design of Large Scale and High Speed Integrated Systems"[49] and on June 3, 1999, Tekn. Lic. Atila Alvandpour defended his doctoral thesis entitled "Power Estimation and Low Power CMOS Circuit Techniques" [48]. In Sept. 1999, Magnus Danestig defended his licentiate thesis "Microwave Filters and Receivers for Adaptive Radar" [45], Peter Hazucha defended his licentiate thesis "Neutron-Induced Soft Errors in CMOS Circuits" [46] and Robert Malmqvist defended his licentiate thesis "Theoretical Analysis of Recursive Active Microwave Integrated Filters" [47].

Dake Liu gave one graduate course during 1999, DSP Processor Design and Implementation Methodology, 5+5 p [50, 51, 52]. Dake Liu has also given guest lectures in Advanced Issues in Computer Architecture, a graduate course offered by the Dept. of Computer Science.

Undergraduate education

During 1999, we have given four courses in the undergraduate programs, for master's students in Applied Physics and Electrical Engineering (the Y program) as well as in Computer Engineering and Science (the D program). The courses are Semiconductor Technology (Per Larsson-Edefors) [56, 58], VLSI Design (Per Larsson-Edefors) [54, 57], Evaluation of an Integrated Circuit (Per Larsson-Edefors) [55] and High-Speed Electronics (Dake Liu) [53, 59, 60]. Per Larsson-Edefors has also given guest lectures in two courses in the D program; Modern Physics and Electromagnetics.

Per Larsson-Edefors has served as a member of the study board for the master's programs in Computer Engineering and Science, Information Technology and Computer Science, respectively, and is also responsible for the Physical Electronics branch of study in the Applied Physics and Electrical Engineering program. Furthermore, Per Larsson-Edefors has concluded the work on reforming the undergraduate education in electronics at LiTH.


Professor Christer Svensson together with Associate Professors Per Larsson-Edefors and Dake Liu as well as Adjunct Professor Staffan Rudner headed the research of the division. The division contains the following research areas:
  • CMOS-Based Low-Power Electronics
  • High-Frequency Wide-Bandgap Semiconductor Power Devices
  • High-Speed CMOS Techniques
  • Infrared Image Sensors
  • Mixed-Signal Circuits
  • Neutron-Induced Soft Errors in Electronics
  • The Next Generation System-on-Chip
  • The research activities are mainly financed through external grants from several sources:
        We participate in two graduate schools, financed by the Foundation for Strategic Research (SSF): ECSEL and INTELECT. ECSEL is a local graduate school aimed at Computer Science and Systems Engineering and INTELECT is a national graduate school in Integrated Electronics. INTELECT was formed out of a proposal by Christer Svensson.
        We also participate in a research consortium, financed by SSF: Smart Sensors. Furthermore, we have support from the Swedish Research Council for Engineering Sciences (TFR). We are also supported by industrial grants, one from Intel Corporation and one from Ericsson Mobile Communications AB. Finally, the research has internal support from the faculty; directly, to the Electronic devices' chair, and indirectly through Center for Industrial Information Technology (CENIIT) at Linksöping university.

    Christer Svensson is associate editor of IEEE Journal of Solid-State Circuits and has served in the program committees of the European Solid-State Circuits Conference (ESSCIRC) 1999 and the International Solid-State Circuits Conference (ISSCC) 2000 (European subcommittee). Per Larsson-Edefors served in the program committee of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 1999. Christer Svensson is also a member of the working group for Microelectronics within SSF. Per Larsson-Edefors was elected board member of the Dept. of Physics and Measurement Technology during 1999.

    Christer Svensson has been on a sabbatical at Intel Corp., as of Aug. 1999. Per Larsson-Edefors has been acting head of the division in Christer Svensson's absence. Peter Hazucha has been with Intel Corp. during the summer of 1999. Dr. Liam Marnane, National Microelectronics Research Centre, Ireland, was a visiting scientist with the Electronic devices division Aug. 1999 - Dec. 1999.

    In summary, during 1999 the group has published 13 journal papers and 30 papers in national and international conferences. Two patent applications have been filed.

    Research projects:

    CMOS-Based Low-Power Electronics

    Up until the beginning of the 90s, research and development in integrated microelectronic systems were only concerned with performance measures such as speed and area. During the 90s the problem of power consumption has been identified as the major limitation to further integration on chips.

    There are two main reasons for the large research momentum in the field of low-power electronics:
        The first reason relates to energy consumption reduction, but reducing energy consumption is equivalent to reducing average power consumption as long as a reduced performance is not compensated for by an extended operation time during which power is consumed. Increasing battery life-time in portable applications today is the main motivation for energy consumption reduction, but in a longer term and on a larger scale, the energy consumed by electronic equipment has to be reduced to ensure a sustainable standard of living for mankind.
        The second reason for reducing power consumption is related to problems arising from the high level of integration and the cost associated to the solutions to these problems. The heat dissipation from a microprocessor chip consuming more than 10 W imposes huge problems in cooling the chip; hence, the packaging is very expensive. Moreover, apart from the degraded performance that comes with increased chip temperature, the chip material deteriorates more rapidly in high temperatures than in low, which manifests itself in reduced reliability.

    Circuit-True Power Estimation
    (A Alvandpour, H Eriksson, P Larsson-Edefors)
    The dominant source of power consumption in digital CMOS circuits is the switching power, which is caused by periodic charging and discharging of nodal capacitances. Traditionally this source has been viewed as the only source of power, probably owing to the fact that it is fairly easily described and fairly readily included in electronic design automation strategies. Furthermore, models of switching power, in order to master the complexity of implementation, have been based on very simplified parameters. Since some of the earlier neglected phenomena constitute a fraction of power consumption, which increases continuously, considerations which have been made in the past are no longer suitable. In this project the main goal is to thoroughly investigate and model the "forgotten" circuit-level phenomena, which cause conventional power estimation values to deviate significantly from the true power. An additional incentive for this research is that this deviation will be even more pronounced in future CMOS processes.

    The phenomena of particular interest are short circuits, Miller (mutual) capacitances and undesired signal transitions (glitches). Mature as well as preliminary results show very promising qualities, and the goal of creating both understanding and estimation methods have been accomplished in several critical domains. For example, we have developed a method for extracting short-circuit power consumption and also managed to quantify the impact of Miller capacitance on power consumption.

    RTL Power Estimation
    (A Alvandpour, D Eckerbert, L Marnane, P Larsson-Edefors)
    An important step towards achieving low-power electronics solutions is to make power estimations available to designers as early as possible in the design process. At a behavioral level, very few things are known about the final, physical implementation. Still, this is the level at which the designer makes a comprehensive survey of possible design options. To be able to evaluate the design options, a structural correspondence to the behavioral description is created and this structure often is situated at the Register-Transfer Level (RTL). Traditionally the RTL components have been in focus, whereas interconnects and their impact on power consumption has been poorly investigated.
        Recent results of this project include the development of a design-sensitive wire length estimator [63], where individual wires can be identified and estimated for length although the input data to the estimator is abstract and contains no implementation information. We have not only managed to resolve the individual interconnections from an abstract description, but also reduced the estimation time complexity for a net of N components from O(N2) to O(N) [16]. The difference stems from the fact that only a full placement can compete with our algorithm, and that requires simulated-annealing-based techniques.

    When running simulations at RT level, almost only input and output signals are available. A viable model for the power consumption is the linear regression model, where transitions at the inputs and outputs are weighed against power consumption. To improve the precision of this model, the input/output vectors are stratified into several classes, each of which has its own set of power consumption parameters. Currently in this project, part of our work is devoted to investigating methods for improving the linear regression model [66]. Key issues involve deciding stratification parameters and introduction of physical interaction between RTL components. Also, work on peak power estimation for use at RT level is underway.

    Low-Power Design
    (A Alvandpour, D Eckerbert, H Eriksson, L Marnane, P Larsson-Edefors)
    Design of low-power CMOS circuits is significantly facilitated when the designer has a thorough understanding of all attributes of power consumption. Not only is it possible to find power-efficient solutions in a quick manner, but the resulting implementations have the potential to be power optimal in its true sense.

    At application-specific levels we have three sub projects running:

  • One sub project, which has been pursued recently, is to trade off power for noise. Here, the key is to concurrently analyze application and circuit, to identify parts where an increased amount of inaccuracy can be accepted at the benefit of power reduction [26, 27].
  • The second sub project comprises a low-power high-performance DFT processor, which is under development. A sub set of the processor, including a full processing element, has been designed in a 0.35-um CMOS process and has arrived from fabrication. This design project has the explicit goal of combining a number of power-saving design methods within a novel implementation structure [22].
  • Low-power implementations targeted for FPGAs is the third project. Here, the experience of circuit design has aided us in reconfiguring an FPGA, such that power can be reduced. The power-reduction technique is based on a transformation of arithmetic implementations into bit-interleaved structures, for which SRAM cells can be used as storage elements [37]. The formal foundation of the transformations was given in [1].
  • At circuit level we have been active in three different sub projects:
  • A very power consuming part of large chips is long interconnects or buses. Low-swing implementations usually require additional hardware and large design efforts. We have developed a new low-power driver-receiver circuit for long interconnects [62] as well as a new low-power multi-threshold receiver [61].
  • Aiming for high performance (speed) usually requires extensive partitioning of logic gates, which prohibits good characteristics in power and area. High fan-in precharged gates can extend their complexity into two different directions:

  •     The gate can contain an evaluation network, which has a transistor structure with little degree of stacking but many parallel transistors. Then leakage is a problem (which will get worse in the future) as the keeper transistor under some conditions needs to draw a large amount of current to replenish the charge of the dynamic node. We have developed a low-power circuit technique for designing keepers for high fan-in precharge gates of this type (parallel evaluation transistors) [15].
        The other gate type is the one containing many series transistors sitting in a stack, thus leading to very low speed. We have developed a new sensing element, that can cut down the delay and save power for high fan-in precharge gates of this type (stacked evaluation transistors) [64].
  • Datapath components are key to all electronics design, and pose design difficulties as they require a tight inter-relation between the algorithm of the operation and the circuit structure to function efficiently. We are currently investigating new circuit solutions in known parallel adder and multiplier micro-architectures. By using a new transistor solution for a Manchester carry chain, we have been able to reduce the delay of a 32-bit adder from the 35ns of a conventional one to 5ns; and a saving in power was also effected [69].
  • High-Frequency Wide-Bandgap Semiconductor Power Devices [28, 32, 44]

    (E Janz?én [Materials science], Q Wahab, S Rudner, C Svensson)
    The combination of several advantageous material properties such as high electric breakdown field and high saturation velocity make SiC and GaN promising materials for high power microwave transistors. The high thermal conductivity of SiC also makes it an ideal substrate material for these transistors. Theoretical calculations indicate that SiC MESFETs and GaN-based HEMTs could have output power densities a factor of 5-10 higher than those of standard technologies.

    During 1999 we have performed numerical drift-diffusion simulations using a commercial program, Medici, from Avant Corporation. We have utilized the most recently published model parameters for 4H-SiC to obtain the closest agreement with experimental data. Our simulations showed that the selection of buffer layer doping and thickness affects the transistors drain characteristics significantly. The semi-insulating substrate properties strongly affect the transistor performance if the buffer layer is too thin and low doped. On the other hand, the use of a thick, highly doped buffer layer reduces the drain current significantly. When operating at a drain voltage of 130 V and gate bias of +2 V, the temperature in the channel region can reach 636 K for a device with a 50-um thick semi-insulating substrate connected to a perfect heat sink.

    High-Speed CMOS Techniques

    The data processing capacity of silicon chips is continuously increasing at very high pace. This has been the case since the birth of the integrated circuit around 1960. In recent years, however, several new problems have appeared, which obstruct further speed increase. These difficulties are often related to interconnections, inside and outside of the chip. We have continued our work in direction to even higher speeds, now with these new limiting factors in mind.

    The chip interfaces have become the most important bottleneck to further increase computing capacity. It is simply not possible to deliver enough input data to the processor to fully utilize its capacity. This is clearly demonstrated by the fact that the on-chip clock frequencies now approach 1 GHz, whereas the clock frequency on the boards in most cases is limited to 200 MHz and below.

    The increasing processing capacity of digital processors has also lead to the trend to perform more and more tasks digitally. Still, for the highest speeds or for weak signals, analog processing is necessary. In fact, also in the case of strong signals, as in transmitters, analog processing is needed. Analog signal processing is, of course, also necessary when converting signals between the analog and the digital domain. Typical applications are the input interfaces to analog communication channels, such as wireless channels, long copper wires at high speed and optical fibers.

    It is the objective of this project to develop techniques which better solve actual problems in the above mentioned areas than the solutions of today.

    High-Speed Digital Circuit Techniques
    (F Mu, C Svensson)
    In order to prove the scalability of the circuit techniques we developed earlier, we demonstrated its ability to run at multigigahertz frequencies in an experimental 0.1-um process (in cooperation with IBM) [13]. A new method to support the design of high-performance circuits was proposed [9, 41]. The problem of wire delays in future chips are addressed in several ways; we investigated how to optimize wire-repeater structures [10, 40] and developed a new method for data synchronization in connection to wire delays [11, 38, 39]. A new method for the synthesis of one clock frequency from another was developed [12].

    Several years of work on very high throughput digital circuits was presented as an invited talk at Symposium on VLSI [43].

    High-Speed Digital Chip Interfaces
    (H Bengtson, C Svensson)
    As mentioned above, traditional board clock frequencies are of the order of 200 MHz. We believe that this must be changed. This is the conclusion of recent analyses of high-speed electronics and its future applications in communications, presented as an invited talk at ESSCIRC [42].

    The ultimate limit for the data rate between chips is given by the properties of the transport medium, in this case the printed circuit board. We have therefore developed a new time domain model for printed circuit boards, which allow accurate analysis of signal transfer and accurate prediction of maximum data rates [17]. (This work was performed at Intel Corp., OR, USA). Further studies will include receiver architectures for very high data rates between chips (~10 Gb/s). Concerning the optical alternative to electrical, we performed a comparison study demonstrating that electrical interconnect is preferable at short distances [2].

    Another application for high-speed interfaces occurs in connection to the fast-developing fiber communication. We have initiated a study of the possibility to integrate the photodiode interface in CMOS, by the enrollment of Ph. D. student Håkan Bengtson, halftime employee of Mitel Semiconductors.

    New Circuit Architectures for Radio Frequency
    (R Malmqvist, M Danestig, S Rudner, C Svensson)
    Radio (and microwave) frequency circuits today mostly use traditionally principles, based on inductors and resonators. As inductors and resonators are hard to integrate in integrated circuits, particularly in silicon, it would be very nice to find alternatives. Furthermore, the use of inductors and resonators makes the tunability of the circuits very limited. Active narrow band microwave integrated filters with sufficiently good filter performance in terms of high gain together with low noise, low intermodulation distortion and low temperature sensitivity may facilitate the realization of highly integrated receivers in future adaptive radar systems, for example.

    In close collaboration with the Defence Research Establishment (FOA), we have initiated a study of the possibilities to design high quality, tunable filters /low noise amplifiers utilizing the principle of recursive active filters. We have theoretically investigated how these filter properties depend on filter topology and amplifier design [7, 8, 34, 35, 36]. Starting from the performance requirements of a typical radar receiver we have used our analytical model to find a suitable filter topology. A cascaded second-order recursive active filter based on HEMT amplifiers was found to be a promising candidate to achieve the adequate performance. We are currently studying the practical MMIC implementation of these filters using standard foundry GaAs processes.

    Infrared Image Sensors

    (D Jakonis, U Ringh, C Jansson, C Svensson)
    This project was started in 1993 and has successfully been completed during 1999. The project was a part of the infrared camera consortium and was run in cooperation with the Defence Research Establishment (FOA), FLIR Systems, Acreo and Royal Institute of Technology.

    In the InfraRed (IR) project we were responsible for the investigation and development of suitable readout electronics for an IR sensor based on a microbolometer focal plane array. For this purpose a readout circuit connected to an array of novel high-resolution A/D-converters was developed. This work has been internationally recognized and has produced several publications over the years. The readout operation and performance has been verified with detectors from both Acreo and Defence Science and Technology Organisation in Australia. The IR consortium will continue to use this readout for development and evaluation of new higher performance detector materials, until the end of year 2000, when this consortium is planned to terminate.

    During 1999 a fundamental noise analysis for different degrees of parallelism has been performed, such that an optimum choice of readout structure can be made with respect to noise. This work has resulted in a manuscript for Sensors and Actuators [4].

    Mixed-Signal Circuits

    Basic Properties of A/D-Converters (ADCs)
    (D Jakonis, J-E Eklund, C Svensson)
    There are several ways to theoretically describe an ADC implementation. There are, however, few complete attempts of understanding the circuit aspects of handling signals in an ADC. The goal in this project is to completely model an ADC and understand the cost for A/D conversion. The work has started by studying the properties of the compare operation - a comparator is the fundamental building block in an ADC. The comparator is subject to studies on e.g. power consumption, noise and speed limitations. It is important to understand the relations between e.g. noise and clock frequency.
    A/D-Converter Modeling
    (K Folkesson, J-E Eklund, D Liu, C Svensson)
    An ADC is preferably simulated in a Spice-like circuit simulator. However, this is very time consuming for large circuits. For simulation of large system, there are dedicated simulation tools, which get reasonable simulation time by simplifying the description of the system. But the errors, which originate from ADC non-idealities, can never be studied in such a simulator. We have been attempting to solve this problem by making a Matlab model of an ADC and integrate that into a Frequency-domain RF simulator [29]. Different types of errors in ADCs can then be studied in measurements or Spice simulation. The errors can subsequently be parameterized and included in the Matlab model. The effect of a particular ADC error on the system performance can thus be studied. This work is a cooperation between the Electronic devices division and the Defence Research Establishment (FOA).
    Analog Circuit Techniques
    (M Duppils, J-E Eklund, C Svensson)
    In a sampled data system, there is some degree of freedom to choose to process data in the digital or the analog domain. For narrow-band systems, a filter operation is integrated into the sampling operation. This filter performs the channel selection and the decimation before the A/D conversion takes place. Thus, the cost of A/D conversion is reduced and power is saved. The results have been verified by chip measurements and a number of publications have been output during 1999 [18, 19, 20, 21].
    A/D-Converter Error Modeling and Identification
    (F Gustafsson [Communication systems, Dept of Electrical Engineering], J-E Eklund)
    One of the most troublesome error sources in an ADC is the lack of matching. It is impossible to fabricate two identical components on the same chip, which for example causes problem in reference-voltage generation. It is obvious that such static errors can be identified and corrected, but to carry out this in a practical way is, however, not trivial. We are developing a concept, which is independent of trimming and calibration signals [23, 24, 67]. Here, the A/D converter is plugged into the target application, and in place it adapts to the environment and performs the A/D conversion correctly. This work is a cooperation between the Electronic devices division, Communication systems at Dept. of EE, and Ericsson Components AB.

    Neutron-Induced Soft Errors in Electronics

    (P Hazucha, K Johansson, C Svensson)
    Integrated circuits continue to improve at a very high pace. The strongest factor in this development is the downscaling of geometry and supply voltage, which has been going on since the 60s. In order to predict and understand the future developments in the field, it is essential to understand the physical limits to downscaling. One of the least understood limits to downscaling is the increased error rate caused by natural cosmic radiation. We therefore initiated a study of these effects in collaboration with Ericsson-Saab Avionics, and later Intel Corp.

    The dominating cosmic radiation in the atmosphere (including ground) is neutron radiation. The neutron flux gives rise to so-called single event upsets, or soft errors, in electronics. As the stored charge in each logical node decreases with decreased dimensions and voltage, the soft error rate will increase. Our objective is to develop methods for the investigation and prediction of these phenomena.

    We have performed measurements on real chips in environments with high neutron flux, at high altitudes (in airplanes) and in artificial neutron flux (The Svedberg Laboratory in Uppsala and Los Alamos Laboratories in New Mexico). We also developed a special test chip for a systematic characterization of the fabrication process [3, 30], and performed process characterization of single event upsets with this chip [31]. We also performed measurements of multiple-bit upsets in SRAMs [5].

    The Next Generation System-on-Chip (SoC)

    This is a new VLSI project performed at the Electronic devices division. The project follows the activity of the SoC cluster, recently proposed by the government. We believe that, in the future, the SoC-level integration is not based on currently available ultra large chip sets. The size of the future intellectual property core (IPR core) will be around 50k gates to satisfy limits from physics, and complexities. The project is focusing on heterogeneous distributed architectures for integrated communications and will demonstrate both domain-specific processors and system-level integration technology at chip level.

    The project is divided into three sub projects:

    Protocol Processor
    (U Nordqvist, T Henriksson, D Liu, C Svensson)
    The computer communication area has developed so rapidly that it left the hardware research lagging behind. The currently available protocol processors are either ASICs, having no flexibility, or RISC based, having low performance. This project aims to bridge the gap between ASIC and RISC, and to demonstrate a unique and configuration-based architecture for protocol processing in digital communications.
        The project was initiated in the beginning of 1999, with the recruitment of Ulf Nordqvist. In Aug. 1999, Tomas Henriksson joined the project. We have published one paper at the 1999 IEEE Workshop on Signal Processing Systems [33], and one manuscript is under development [70]. The project is done in collaboration with SwitchCore AB in Lund and Ericsson Components AB, LME Ericsson Research in Kista-Stockholm.
    System-on-Chip Integration Methodology
    (D Wiklund, D Liu)
    The currently available SoC integration methodology is based on either custom-designed glue logic or on low-performance arbitration-based time-sharing buses. These solutions are far off the requirements for modern communication systems. Since there is a weak data dependency in the communication system, we have a chance to attain a real-time multiple-channel communication on chip level. The aim of this project is to demonstrate a new path to system integration, using a module-based bus and having reduced system verification time.
        The project started in April 1999, and the project pre-study was finished in the end of June. A final year project, under supervision of Dake Liu, commenced in Aug. 1999 and was concluded in December. This project has given a systematic feasibility study on a SoC bus, for a hardware-module-based system for chip integration and communications beyond instruction sets. A manuscript for publication is currently being finalized. A Ph. D. student, Daniel Wiklund, has been recruited and he will start working for the project in Jan. 2000.
    Heterogeneous Digital Signal Processors
    (D Liu, P Larsson-Edefors)
    Modern communication algorithms provide possibilities to perform heterogeneous digital signal processing in parallel. The DSP hardware in communication system still has not made use of this feature, offered by the algorithms. The classical centralized DSP consumes too much computing power and requires too long development time. The classical parallel DSP can not manage the complexity of modern communication jobs. Therefore, this project aims at exploring distributed heterogeneous DSP and to propose a better solution for DSP hardware.
        The project was initiated in June 1999, and was set up in collaboration with Ericsson Mobile Communications AB in Lund. Ericsson has given a donation for senior activities. A final year project, supervised by Dake Liu, started in Aug. 1999. This project is directed towards the SPI, SCI, and Serial ADC compatible common interface, acting as a peripheral for the heterogeneous digital signal processing hardware. The final year project was concluded in Dec. 1999 and a manuscript for publication is in preparation [71].


    A: (International Journals)
    [1]S J Bellis, W P Marnane and P Larsson-Edefors: "Bit Serial, MSB First Processing Units", Intl J. of Electronics, vol. 86, no. 6, pp. 723-38, June 1999.
    [2]E Berglind, L Thylen, B Jaskorzynska and C Svensson: "A Comparison of Dissipated Power and Signal-To-Noise Ratios in Electrical and Optical Interconnects", J. of Lightwave Technology, vol. 17, no. 1, pp. 68-73, Jan. 1999.
    [3]P Hazucha and C Svensson: "Optimized Test Circuits for SER Characterization of a Manufacturing Process", to be published in IEEE J. Solid-State Circuits, Feb. 2000.
    [4]D Jakonis, C Svensson and C Jansson: "Readout Architectures for Uncooled IR Detector Arrays", to be published in Sensors and Actuators A.
    [5]K Johansson, M Ohlsson, N Ohlsson, J Blomgren and P-U Renberg: "Neutron Induced Single-Word Multiple-Bit Upset in SRAM", IEEE Trans. on Nuclear Science, Dec. 1999.
    [6]P Larsson-Edefors: "Investigation on Maximal Throughput of a CMOS Repeater Chain", to be published in IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications.
    [7]R Malmqvist, M Danestig, S Rudner and C Svensson: "Some Limiting Factors for the Noise Optimization of Recursive Active Microwave Integrated Filters", Microwave and Optical Technology Letters, vol. 22, no. 3, pp. 151-7, Aug. 1999.
    [8]R Malmqvist, M Danestig, S Rudner and C Svensson: "Theoretical Analysis of Sensitivity and Q-Value for Recursive Active Microwave Integrated Filters", IEE Proceedings - Microwaves, Antennas and Propagation, vol. 146, no. 4, pp. 247-52, Aug. 1999.
    [9]F Mu and C Svensson: "A Layout-Based Schematic Method for Very High-Speed CMOS Cell Design", IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 144-8, March 1999.
    [10]F Mu and C Svensson: "Analysis and Optimization of a Uniform Long Wire and Driver", IEEE Trans. on Circuits and Systems I: Fundamental Theory and Applications, vol. 46, no. 9, pp. 1086-1100, Sept. 1999.
    [11]F Mu and C Svensson: "Vector Transfer by Self-Tested Self-Synchronization for Parallel Systems", IEEE Trans. on Parallel and Distributed Systems, vol. 10, no. 8, pp. 769-80, Aug. 1999.
    [12]F Mu, A Edman and C Svensson: "Digital Multiphase Clock/Pattern Generator", IEEE J. of Solid-State Circuits, vol. 34, no. 2, pp. 182-91, Feb. 1999.
    [13]J Yuan and C Svensson: "Multigigahertz TSPC Circuits in Deep Submicron CMOS", Physica Scripta, T79, pp. 283-6, 1999.
    C: (Popular science)
    [14]P Larsson-Edefors: "Professorer bland processorer", invited paper in Sommarutskick 1999 - läsvärda texter för dig som ska börja på Y, pp. 12-3, 1999.
    D: (Conferences)
    [15]A Alvandpour, P Larsson-Edefors and C Svensson: "A Leakage-Tolerant Multi-Phase Keeper for Wide Domino Circuits", Proc. of the 6th IEEE Intl Conf. on Electronics, Circuits and Systems, vol. I, pp. 209-12, Pafos (Cyprus), Greece, Sept. 5-8 1999.
    [16]A Alvandpour, P Larsson-Edefors and C Svensson: "GLMC: Interconnect Length Estimation by Growth-Limited Multifold Clustering", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.
    [17]G Dermer and C Svensson: "Time Domain Modeling of Lossy Interconnects", to be presented at 2nd IMAPS Advanced Technology Workshop: Future Digital Interconnects over 1,000 MHz, Austin, TX, USA, Jan. 17-18 2000.
    [18]M Duppils, J-E Eklund and C Svensson: "A Novel Mixed Analog/Digital MAC Unit Implemented with SC Technique Suitable for Fully Programmable Narrow-Band FIR Filter Applications", Proc. of IEEE Intl Conf. on Electronics, Circuits and Systems, pp. 1197-200, Pafos (Cyprus), Greece, Sept. 5-8 1999.
    [19]M Duppils, J-E Eklund and C Svensson: "A Study of the Non-Ideal Properties of Sample-and-Hold Circuits with Respect to the Analog Bandwidth", Proc. of the 3rd IEE Intl Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 119-21, Glasgow, UK, July 27-28 1999.
    [20]M Duppils, J-E Eklund and C Svensson: "Realization of Fully Programmable Narrow-Band FIR Filters with SC Technique", Proc. of Midwest Symp. on Circuits and Systems, Las Cruces, NM, USA, Aug. 1999.
    [21]M Duppils: "A Mixed Analog/Digital Multiply-Accumulate Unit Suitable for Implementation with CMOS Technology", Proc. of the 2nd Conf. on Computer Science and Systems Engineering in Linköping, pp. 101-7, Norrköping, Sweden, Oct. 21-22 1999.
    [22]D Eckerbert, H Eriksson, P Larsson-Edefors and A Edman: "An Interconnect-Driven Design of a DFT Processor", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.
    [23]J-E Eklund and F Gustafsson: "Digital Offset Compensation of Time-Interleaved ADC Using Random Chopper Sampling", to be presented at IEEE Intl Symp. on Circuits and Systems, Geneva, Switzerland, 2000.
    [24]J-E Eklund: "Randomization for Error Identification in ADC", to be presented at GigaHertz 2000.
    [25]J-E Eklund: "Robust ADC Concept for Integrated CMOS Systems", Proc. of the 3rd IEE Intl Conf. on Advanced A/D and D/A Conversion Techniques and Their Applications, pp. 126-9, Glasgow, UK, July 27-28 1999.
    [26]H Eriksson, A Edman and P Larsson-Edefors: "Multiplexer-Based Low-Power Phase Accumulator", Proc. of RadioVetenskap och Kommunikation 99, pp. 323-7, Karlskrona, Sweden, June 14-17 1999.
    [27]H Eriksson, P Larsson-Edefors and A Edman: "Using Clock Division to Reduce Power Consumption", Proc. of the 9th Intl Workshop on Power and Timing Modeling, Optimization and Simulation, pp. 211-20, Kos Island, Greece, Oct. 6-8 1999
    [28]J Eriksson, N Rorsman, H Zirath, Q Wahab and S Rudner: "SiC Microwave Power Transistors", Proc. of RadioVetenskap och Kommunikation 99, pp. 216-20, Karlskrona, Sweden, June 14-17 1999.
    [29]K Folkesson, J-E Eklund, C Svensson and A Gustafsson, "A Matlab-Based ADC Model for RF System Simulations", to be presented at GigaHertz 2000.
    [30]P Hazucha and C Svensson: "Circuit Technique for Accurate Soft Error Rate Measurements", Proc. of the 25th European Solid-State Circuits Conf., pp. 190-3, Duisburg, Germany, Sept. 21-23 1999.
    [31]P Hazucha and C Svensson: "Experiment-Based Methodology for Modeling of SER in Modern CMOS Technologies", Proc. of the 2nd Conf. on Computer Science and Systems Engineering in Linköping, pp. 93-100, Norrköping, Sweden, Oct. 21-22 1999.
    [32]R Jonsson, Q Wahab and S Rudner: "Physical Simulations on the Operation of 4H-SiC Microwave Power Transistors", Proc. of the Intl Conf. on Silicon Carbide and Related Materials, Research Triangle Park, NC, USA, Oct. 10-15 1999.
    [33]D Liu, U Nordqvist and C Svensson: "Configuration Based Architecture for High Speed and General Purpose Protocol Processing", Proc. of IEEE Workshop on Signal Processing Systems, Taipei, Taiwan, ROC, Oct. 20-22 1999.
    [34]R Malmqvist, M Danestig, S Rudner and C Svensson: "Analysis of Intermodulation and Noise Performance for Recursive Active Microwave Integrated Filters", Proc. of the 29th European Microwave Conf., pp. 60-3, Munich, Germany, Oct. 4-8 1999.
    [35]R Malmqvist, M Danestig, S Rudner and C Svensson: "Estimation of Spurious-Free Dynamic Range for Recursive Active Microwave Integrated Filters", Proc. of the Asia Pacific Microwave Conf., Singapore, Nov. 30 - Dec. 3 1999.
    [36]R Malmqvist, A Gustafsson, M Danestig, S Rudner and C Svensson: "Noise and Temperature Behavior of Tunable Recursive Active MMIC-Filters for On-Chip Microwave Receivers", Proc. of RadioVetenskap och Kommunikation 99, pp. 232-6, Karlskrona, Sweden, June 14-17 1999.
    [37]W P Marnane, S J Bellis, F Murra, P Larsson-Edefors and E M Popovici: "Bit-Serial, Bit Interleaved Processing - An Area/Power Efficient Architecture for SRAM FPGAs", to be presented at 8th ACM Intl Symp. on Field-Programmable Gate Arrays, Monterey, CA, USA, Feb. 2000.
    [38]F Mu and C Svensson: "A 750 Mb/s 0.6 um CMOS Two-Phase Input Port Using Self-Tested Self-Synchronization", IEEE Intl Solid-State Circuits Conf., Digest of Technical Papers, pp. 178-9, San Francisco, CA, USA, Feb. 15-17 1999.
    [39]F Mu and C Svensson: "High Speed Interface for System-on-Chip Design by Self-Tested Self-Synchronization", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 2, pp. 516-9, Orlando, FL, USA, May 30 - June 2 1999.
    [40]F Mu and C Svensson: "High Speed Multistage CMOS Clock Buffers with Pulse Width Control Loop", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 2, pp. 541-4, Orlando, FL, USA, May 30 - June 2 1999.
    [41]F Mu and C Svensson: "Methodology of Layout Based Schematic and Its Usage in Efficient High Performance CMOS Design", Proc. of IEEE Intl Symp. on Circuits and Systems, vol. 6, pp. 254-7, Orlando, FL, USA, May 30 - June 2 1999.
    [42]C Svensson: "High Speed Electronics Interfacing Fiber Networks", Proc. of the 25th European Solid-State Circuits Conf., p. 21, Duisburg, Germany, Sept. 21-23 1999.
    [43]C Svensson and A Edman: "10-100 Gb/s Throughput CMOS Techniques", 1999 Symp. on VLSI Circuits, Digest of Technical papers, pp. 65-8, Kyoto, Japan, June 17-19 1999.
    [44]Q Wahab, S Rudner and E Janzén: "Power Schottky Rectifiers and Microwave Transistors in 4H-SiC", Proc. of the 10th Intl Workshop on the Physics of Semiconductor Devices, New Delhi, India, Dec. 14-18 1999.
    F: (Theses)
    [45]M Danestig: Microwave Filters and Receivers for Adaptive Radar, Linköping studies in science and technology, Licentiate Thesis 785, Sept. 1999.
    [46]P Hazucha: Neutron-Induced Soft Errors in CMOS Circuits, Linköping studies in science and technology, Licentiate thesis 768, Sept. 1999.
    [47]R Malmqvist: Theoretical Analysis of Recursive Active Microwave Integrated Filters, Linköping studies in science and technology, Licentiate thesis 777, Sept. 1999
    [48]A Alvandpour: Power Estimation and Low Power CMOS Circuit Techniques, Linköping studies in science and technology, Dissertation 587, ISBN 91-7219-503-7, June 1999.
    [49]F Mu: Design of Large Scale and High Speed Integrated Systems, Linköping studies in science and technology, Dissertation 564, ISBN 91-7219-414-6, Feb. 1999.
    G: (Postgraduate course material)
    [50]D Liu: "A Simplified FIR IIR Core", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.
    [51]D Liu: "Design Methodology for DSP Processors, Part One: Functional Design", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.
    [52]D Liu: "Design Methodology for DSP Processors, Part Two: ASIC Implementation", compendium in Digital signal processor design and implementation methodology, graduate course, 1999.
    H: (Undergraduate course material)
    [53]M Duppils: "Measurement on Receiver Building Blocks", laboratory manual in TFFY71 High-speed electronics, undergraduate course, Oct. 1999.
    [54]D Eckerbert, H Eriksson, "VLSI Design 2000", laboratory manual in TFFY90 VLSI design, undergraduate course, Dec. 1999.
    [55]P Larsson-Edefors and C Svensson: "Evaluation of an Integrated Circuit", compendium in TFFY94 Evaluation of an integrated circuit, undergraduate course, Oct. 1999.
    [56]P Larsson-Edefors: "Semiconductor Technology", compendium in TFFY34 Semiconductor technology, undergraduate course, Oct. 1999.
    [57]P Larsson-Edefors: "VLSI Design", collection of presentation transparencies in TFFY90 VLSI design, undergraduate course, May 1999.
    [58]P Larsson-Edefors, P Hazucha, "Semiconductor Technology - Laboratory Exercises", laboratory manual in TFFY34 Semiconductor technology, undergraduate course, Oct. 1999.
    [59]D Liu: "High-Speed Electronics", collection of presentation transparencies in TFFY71 High-speed electronics, undergraduate course, Dec. 1999.
    [60]R Malmqvist: "Characterization of a Low Noise Amplifier", laboratory manual in TFFY71 High-speed electronics, undergraduate course, Oct. 1999.
    I: (Manuscripts)
    [61]A Alvandpour, P Larsson-Edefors and C Svensson: "A High-Speed, Low-Power Interconnect Architecture", manuscript.
    [62]A Alvandpour, P Larsson-Edefors and C Svensson: "A Low-Power, High-Speed and Robust Clocked Driver-Receiver Circuit for Long On-Chip Interconnects", manuscript.
    [63]A Alvandpour, P Larsson-Edefors and C Svensson: "Design-Sensitive Interconnection Length Estimation", submitted.
    [64]A Alvandpour, P Larsson-Edefors and C Svensson: "Fast and Energy-Efficient Sensing Elements for High Fan-In Domino Gates", manuscript.
    [65]R Arvidsson, M Duppils and J-E Eklund: "Switched Capacitors", Swedish patent application no. 902253-5.
    [66]D Eckerbert, P Larsson-Edefors, and A Alvandpour: "Circuit-Level Considerations for Power Macro Modeling", manuscript.
    [67]J-E Eklund and F Gustafsson: "Offsetkompensering i analog-till-digitalomvandlare", Swedish patent application no. 9901233-8.
    [68]J-E Eklund and C Svensson: "Influence of Metastability Errors on SNR in Successive-Approximation A/D Converters", manuscript.
    [69]H Eriksson, A Alvandpour and P Larsson-Edefors: "A Sensing-Element Approach to High-Speed Manchester Adders", submitted.
    [70]T Henriksson and D Liu: "Early Partitioning of the Control for a General Purpose Protocol Processor", manuscript.
    [71]D Liu and A Arvidsson: "SCI, SPI and Serial ADC Interface Compatible Core", manuscript.